The present invention relates to a logic analyzer for analyzing logic data from a logic circuit including a microprocessor.
For developing, manufacturing or troubleshooting complex digital electronic apparatus having incorporated thereinto, for example, a microprocessor, logic measurement instruments are necessary which makes it possible to observe the state of input and output logic data of respective parts and logic data such as a program for operating the apparatus. One logic measurement instrument is a logic analyzer. The logic analyzer of this kind is disclosed, for instance, in "Hewlett-Packard Journal" (pp. 2-9, January 1974) and U.S. Pat. Nos. 4,425,643 (issued on Jan. 10, 1984) and 4,434,488 (issued on Feb. 28, 1984). In this logic analyzer, input logic data is stored in a data memory and the stored data is displayed on a CRT display or the like for effecting program analyses such as a state analysis and a timing analysis of the input logic data. As compared with other logic measurement instruments, the logic analyzer is a very useful and versatile measurement instrument because it can detect a desired word (referred to as a trigger word) from the input digital data and can measure a desired portion of the input digital data on the basis of the desired word.
To facilitate a better understanding of the present invention, a description will be given first, with reference to FIGS. 1 and 2A to 2F, of a conventional logic analyzer. Input digital data, which consists of a plurality of parallel bits, is applied from a data acquisition probe 10 to a level converter 11, wherein its level is compared with a reference level and converted to a logic level suitable for handling in the logic analyzer. The input digital data from the level converter 11 is applied to a temporary memory 12. A sampling pulse generator 14 applies sampling pulses 101 to the temporary memory 12 and the input digital data (hereinafter referred to simply as the input data) is input in the temporary memory 12 at the timing of the sampling pulse and held there until the next sampling pulse is applied.
The sampling pulse 101, for example, in the case of a state analysis, is generated by the sampling pulse generator 14 based on a clock signal which is applied from a logic circuit under test, such as an electronic apparatus, and in the case of a timing analysis, clock signals are used which are generated, by a clock signal generator built in the logic analyzer, at a higher rate than the repetition rate of the input data and at regular intervals.
The data held in the temporary memory 12 is applied to a data memory 13 and a trigger word detecting part 16. The data memory 13 loads thereinto the data from the temporary memory 12 at an address specified by an address signal from an address counter 15. The address counter 15 is supplied with the sampling pulses 101 from the sampling pulse generator 14 and advances by one step upon each application of the sampling pulse 101. The count output of the address counter 15 is applied as the address signal to the data memory 13.
The trigger word detecting part 16 is given a predetermined trigger word in advance, and it compares the trigger word with the data from the temporary memory 12 and, in the case of coincidence, applies a coincidence signal 110 to a delay setting part 26 which serves as a delay means. Supplied with the coincidence signal 110, the delay setting part 26 starts to count the sampling clocks 101 and generates a stop signal 103 when it counts a preset number of pulses. That is, the stop signal 103 is generated a certain period of time after the generation of the coincidence signal 110 and the signal 103 is applied to the address counter 15. As a result of this, the step-by-step operation of the address counter 15 stops, bringing the input data loading operation of the data memory 13 to an end. In other words, when a predetermined number of data are loaded into the data memory 13 after appearance of the trigger word in the input data, the loading operation is stopped.
Based on an instruction from a control unit 19 which is formed by a microcomputer, the data thus loaded into the data memory 13 is provided via an interface bus 32 to the control unit 19, wherein the data is read out over a desired range on the basis of the trigger word, thereafter being displayed on a display 18. More specifically, the address counter 15 is controlled by the control unit 19 to generate an address signal necessary for readout of the data memory 13. The data read out of the data memory 13 by the address signal is transferred via the interface bus 32 to the control unit 19, wherein the transferred data is converted into various display formats necessary for a logic analysis and then displayed on the display 18.
The control unit 19 exerts control over the entire operation of the logic analyzer, that is, it controls the readout of data from the data memory 13 and the display format as mentioned above and, at the start of measurement, controls the application of a trigger word specified through a keyboard 17 to a register in the trigger word detecting part 16 via the bus 32 and the setting in the delay setting part 26 of a number corresponding to a required delay time so as to determine how many times data is to be acquired prior to the generation of the stop signal after the detection of the trigger word from the sampled data.
FIGS. 2A to 2F show a timing chart for explaining the input data acquiring operation and the stored contents of the data memory 13 in the conventional logic analyzer shown in FIG. 1. By repetitive generation of the sampling pulse 101 the data 102 held in the temporary memory 12 is loaded into the data memory 13 and, at the same time, new input data is sampled and held in the temporary memory 12. The data memory 13 has, for example, 1024 words and writes therein the data 102 starting at an address 0 until the stop signal is applied thereto from the delay setting part 26. When the stop signal 103 is not applied after the data is written at an address 1023, the write returns to the address 0. That is, the data 102 is continuously written into the data memory 13 until the stop signal 103 is generated, and the old contents of the data memory 13 are renewed by the up-to-date data.
In this example, it is assumed that the trigger word T is applied to the trigger word detecting part 16 prior to measurement. The data 102 is loaded by the sampling pulses 101 into the data memory 13 at respective addresses one after another, and when a word that appears in the data 102 coincides with the word T, the trigger word detecting part 16 detects the coincidence, and yields a coincidence signal 110, and after the lapse of time t the delay setting part 26 generates the stop signal 103. The stop signal stops the step-by-step operation of the address counter 15, after which the data memory 13 is not accessed.
In this way, the data continuously loaded into the data memory 13 is provided, under control of the control unit 19, via the interface bus 32 to the control unit 19, wherein a required portion of the data is read out on the basis of the trigger word T, and the read-out data is converted into a display format suitable for a logic analysis, thereafter being displayed on the display 18.
As described above, the prior art logic analyzer specifies one trigger word and performs storage and display of the input data on the basis of the trigger word. Therefore, the utilization efficiency of the data memory 13 is low, and when it is desired to carry out a logic analysis using a plurality of trigger words, it is necessary to set the trigger words one by one and to repeat measurement. Accordingly, the conventional logic analyzer requires much time for the logic analysis and encounters difficulty in conducting a complex logic analysis.